USB97C201 datasheet(52/59 Pages) SMSC

52 / 59 page

SMSC DS – USB97C201

Page 52

Rev. 03/25/2002

PRELIMINARY

RAMRD_

TOGGLE

Written?

Yes

RAMRD_

TOGGLE=

Yes

RAMRD_A=0;

Begin

Output A Buffer

SRAM Data

RAMRD_

TOGGLE

Written?

Yes

POR

RAMRD_A=1

RAMRD_B=1

Output

Completed?

Yes

RAMRD_A=1

RAMRD_

TOGGLE=

Yes

RAMRD_B=0;

Begin

Output B Buffer

SRAM Data

RAMRD_

TOGGLE

Written?

Output

Completed?

Yes

RAMRD_B=1

RAMRD_

TOGGLE=

Yes

OUTPUT

FLOW CONTROL

ACTIVE

OUTPUT

FLOW CONTROL

INACTIVE

RAMRD_B=0

RAMRD_B=0?

Yes

RAMRD_A=0

RAMRD_A=0?

Yes

FIGURE 4 - TRANSMIT BUFFER OPERATION

Transmit buffer operations are always initiated by writing the RAMRD_TOGGLE bit in the EP2 Control register.

Output flow control to the device receiving data from the SRAM buffer is active once data in both buffers has been

transferred. If the destination is the SIE, then it will NYET or NAK further INs. If it is the ATA interface, nDAK will not

be asserted in response to DRQ data will not be clocked out.

6.9.3

AUTOMATIC TRANSFER OPERATION

If the AUTO_TRANS bit is set in the ATA_CTL register, then automatic manipulation of the RAMWR_TOGGLE,

RAMRD_TOGGLE, RAMWR_B, and RAMWR_A bits is executed by a state machine to allow continuous streaming

of the data between EP2 and the ATA DMA interface. Automatic transfer of byte counts between the

RAMWRBC_A/B and RAMRDBC_A/B registers is also implemented. This is illustrated in Figure 5.

Note: If the count in RAMWRBC_A/B is zero, no transfer will occur. This is likely to happen on transfers from the SIE

to the ATA at the very end of the transfer.

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