AD8021 datasheet(15/32 Pages) AD

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AD5429/AD5439/AD5449

Rev. 0 | Page 15 of 32

GENERAL DESCRIPTION

The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit dual-

channel current output DACs consisting of a standard inverting

R−2R ladder configuration. A simplified diagram of one DAC

channel for the AD5449 is shown in Figure 36. The feedback

resistor RFB has a value of R. The value of R is typically 10 kΩ

(minimum 8 kΩ and maximum 12 kΩ). If IOUT1 and IOUT2 are

kept at the same potential, a constant current flows in each

ladder leg, regardless of digital input code. Therefore, the input

resistance presented at VREF is always constant.

S12

DAC DATA LATCHES

AND DRIVERS

RFBA

IOUT1A

IOUT2A

VREFA

Figure 36. Simplified Ladder

Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of

the DACs, making the devices extremely versatile and allowing

them to be configured in several operating modes, such as

unipolar mode, bipolar output mode, or single-supply mode.

UNIPOLAR MODE

Using a single op amp, these devices can easily be configured to

provide 2-quadrant multiplying operation or a unipolar output

voltage swing, as shown in Figure 37.

When an output amplifier is connected in unipolar mode, the

output voltage is given by

REF

OUT

−

where D is the fractional representation of the digital word

loaded to the DAC, and n is the number of bits.

D = 0 to 255 (AD5429)

= 0 to 1023 (AD5439)

= 0 to 4095 (AD5449)

With a fixed 10 V reference, the circuit shown in Figure 37 gives

a unipolar 0 V to −10 V output voltage swing. When VIN is an ac

signal, the circuit performs 2-quadrant multiplication.

Table 5 shows the relationship between digital code and the

expected output voltage for unipolar operation for the AD5429.

Table 5. Unipolar Code Table

Digital Input

Analog Output (V)

1111 1111

−VREF (4095/4096)

1000 0000

−VREF (2048/4096) = −VREF/2

0000 0001

−VREF (1/4096)

0000 0000

−VREF (0/4096) = 0

AD5429/

AD5439/

AD5449

NOTES:

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

3. DAC B OMITTED FOR CLARITY.

IOUT1A

IOUT2A

VREF

VDD

VOUT = 0V TO –VREF

AGND

VDD

VREF

SDIN

GND

SCLK

SYNC

µCONTROLLER

RFBA

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 37. Unipolar Operation

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