Data Sheet

AD5624/AD5664

Rev. A | Page 7 of 23

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

10

2

9

3

GND

8

DIN

4

7

SCLK

5

6

SYNC

AD5624/

AD5664

TOP VIEW

(Not to Scale)

Figure 3. 10-Lead MSOP Pin Configuration

GND

DIN

SCLK

SYNC

1

2

3

4

5

10

NOTES

1. EXPOSED PAD TIED TO GND

ON LFCSP PACKAGE.

9

8

7

6

AD5624/

AD5664

TOP VIEW

(Not to Scale)

Figure 4. 10-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

3

GND

Ground Reference Point for All Circuitry on the device

4

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

5

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

6

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on

the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next

write sequence is ignored by the device.

7

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 50 MHz.

8

DIN

Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of

the serial clock input.

9

Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. The supply is decoupled with a 10 μF

capacitor in parallel with a 0.1 μF capacitor to GND.

10

Reference Voltage Input.

EPAD

Exposed Pad. Exposed pad tied to GND on LFCSP package.