AX88875AP Bripeater

ASIX ELECTRONICS CORPORATION

16

4.0 INTERNAL REGISTERS

4.1 Configuration Register (CONFIG)

Bit

Bit Name

Access

Bit Description

D9

/HALF10

R/W

Half-duplex mode in 10Mbps : “low” resister to 10Mbps PHY in half-

duplex mode. “high” resister to 10Mbps PHY in full-duplex mode.

D8

OPT[4]

R/W

OPT[4] : Option for external device type to connect to port 4. Default

‘high’ is for PHY type device. Otherwise, ‘low’ for bridge, switch or

MAC type device.

D7

TXM_MODE

R/W

TXM_MODE : Option for internal used. Default ‘high’ user may pull the

pin ‘low’ with 10K ohm resister for reserve transmition mode alternaty.

D6

MODE

R/W

MODE

= 0 : Single chip repeater application.

MODE

= 1 : Multiple chips cascaded repeater application.

D5

EN_FLOW_

CTL

R/W

EN_FLOW_CTL = 0 : Disable flow control function.

EN_FLOW_CTL = 1 : Enable flow control function.

D4

ST_FW

R/W

ST_FW

= 0 : fragment-free mode

ST_FW

=1 : Store-n-Forward mode

D3

ENTRIES

R/W

ENTRIES

= 0 : 1024 entries supported

ENTRIES

= 1 : 256 entries supported

D2-1

MEM_SIZE[1]

MEM_SIZE[0]

R/W

MEM_SIZE[1] MEM_SIZE[1]

SIZE (K)

1

1

32K

1

0

64K

0

1

128K

0

0

N/A

D0

/IR_ACT_EN

R/W

Inter Repeater Active Input Pin Enable : Designer must keep the pin pull

high to disable the function.