DM562AP
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
Preliminary
27
Version: DM562AP-DS-P02
March 05, 2004
Command Register Definition:
15
10
987
654
3
21
0
Reserved
R/W
0
R/W
00
R/W
R/W
R/W
0
0
Parity Error Response Enable/Disable
I/O Space Access Enable/Disable
Memory Space Access Enable/Disable
Master Device Capability Enable/Disable
SERR# Driver Enable/Disable
Mast Mode Fast Back-To-Back
Address/Data Steeping
VGA Palette snoop
Special Cycle
Memory Write and Invalid
Bit
Default
Type
Description
15:10
000000
RO
Reserved
90
RO
Master Fast Back-to-back Mode (0 For No Support)
The DM6588A does not support master mode fast back-to-back capability
and will not generate fast back-to-back cycles.
80
RW
SERR# Driver Enable/Disable
This bit controls the assertion of SERR# signal output. The SERR# output
will be asserted on detection of an address parity error and if both this bit
and bit 6 are set.
70
RO
Address/Data Stepping (0 For No Stepping)
60
RW
Parity Error Response Enable/Disable
Setting this bit will enable the DM6588A to assert PERR# on the detection
of a data parity error and to assert SERR# for reporting address parity error.
50
RO
VGA Palette Snooping (0 For No Support)
40
RO
Memory Write and Invalid (0 For No Support)
30
RO
Special Cycles (0 For No Implementation)
20
RW
Master Device Capability Enable/Disable
The DM6588A will never support the function.
10
RW
Memory Space Access Enable/Disable
The DM6588A will never support the function.
01
RW
I/O Space Access Enable/Disable
This bit controls the ability of I/O space access.
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