COP8-NSDEV datasheet(46/83 Pages) NSC

46 / 83 page

14.0 USART (Continued)

14.6 USART INTERRUPTS

The USART is capable of generating interrupts. Interrupts

are generated on Receive Buffer Full and Transmit Buffer

Empty. Both interrupts have individual interrupt vectors. Two

bytes of program memory space are reserved for each in-

terrupt vector. The two vectors are located at addresses

0xEC to 0xEF Hex in the program memory space. The

interrupts can be individually enabled or disabled using En-

able Transmit Interrupt (ETI) and Enable Receive Interrupt

(ERI) bits in the ENUI register.

The interrupt from the Transmitter is set pending, and re-

mains pending, as long as both the TBMT and ETI bits are

set. To remove this interrupt, software must either clear the

ETI bit or write to the TBUF register (thus clearing the TBMT

bit).

The interrupt from the receiver is set pending, and remains

pending, as long as both the RBFL and ERI bits are set. To

remove this interrupt, software must either clear the ERI bit

or read from the RBUF register (thus clearing the RBFL bit).

14.7 BAUD CLOCK GENERATION

The clock inputs to the transmitter and receiver sections of

the USART can be individually selected to come either from

an external source at the CKX pin (port L, pin L1) or from a

source selected in the PSR and BAUD registers. Internally,

the basic baud clock is created from the MCLK through a

two-stage divider chain consisting of a 1-16 (increments of

0.5) prescaler and an 11-bit binary counter (Figure 23). The

divide factors are specified through two read/write registers

shown in Figure 24. Note that the 11-bit Baud Rate Divisor

spills over into the Prescaler Select Register (PSR). PSR is

cleared upon reset.

As shown in Table 20, a Prescaler Factor of 0 corresponds to

NO CLOCK. This condition is the USART power down mode

where the USART clock is turned off for power saving pur-

pose. The user must also turn the USART clock off when a

different baud rate is chosen.

The correspondences between the 5-bit Prescaler Select

and Prescaler factors are shown in Table 20. There are

20006326

FIGURE 22. Framing Formats

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