LTC4216IDE datasheet(15/24 Pages) LINER

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LTC4216

4216f

Figure 9. Normal Power-Up Sequence (with Analog Current Limiting)

SENSEP

TIMER

GATE

VOUT

ILOAD

FILTER

RESET

VCC

POWER GOOD

VFB > 0.6V

LOAD CURRENT REGULATING

AT 40mV/RSENSE

POWER BAD

VFB < 0.6V

(VGATE – VOUT) > VGS(TH)

(VSENSEP – VSENSEN) > 25mV

FILTER RAMPS UP WHEN (VSENSEP – VSENSEN) > 25mV

OUTPUT IN ANALOG CURRENT LIMIT,

(VSENSEP – VSENSEN) = 40mV

(VSENSEP – VSENSEN) < 25mV

TRACKS SS RAMP

IN REGULATION

20µA

60µA

2.4µA

VTMR(TH)

2µA

VTMR(TH)

2µA

10µA

1µA

CHECK FOR GATE,

FILTER, TIMER,

SS < 0.2V

CHECK FOR GATE, FILTER, TIMER, SS < 0.2V AND FAULT HIGH

PLUG-IN CYCLE

FIRST TIMING CYCLE

POWER-GOOD DELAY

SECOND TIMING CYCLE

4216 F09

5 6

7 8

9 10 11

0.72V

0.4V

0.8V

ELECTRONIC CIRCUIT BREAKER ARMED

RESET

GOES HIGH

IN RESET

MODE

(ON < 0.4V)

ON GOES LOW

(ON < 0.72V)

OUTPUT NO LONGER

IN CURRENT LIMIT

RESET PULLED LOW

DUE TO POWER BAD

2ND TIMING CYCLE CANNOT START WITH

OUTPUT IN ANALOG CURRENT LIMIT

VFILT(TH)

APPLICATIO S I FOR ATIO

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