AD5544ACPZ-1-R2 datasheet(18/24 Pages) AD

18 / 24 page

AD5544/AD5554

Data Sheet

Rev. H | Page 18 of 24

INPUT

DAC A

2:4

DECODE

D10

D11

D12

D13

D14

D15

DAC D

DAC C

DAC B

DAC A

POWER-

RESET

DAC B

DAC C

DAC D

DAC A

AD5544

VREFA B C D

VDD

RFBA

IOUTA

AGNDA

RFBB

IOUTB

AGNDB

RFBC

IOUTC

AGNDC

RFBD

IOUTD

AGNDD

AGNDF

DGND

MSB

VSS

SET

MSB

SET

MSB

SDO

SDI

CLK

LDAC

Figure 23. System Level Digital Interfacing

SHIFT REGISTER

ADDRESS

DECODER

TO INPUT REGISTER

19TH/17TH

CLOCK

SDO

SDI

CLK

Figure 24. AD5544/AD5554 Equivalent Logic Interface

POWER-ON RESET

When the VDD power supply is turned on, an internal reset strobe

forces all the input and DAC registers to the zero-code state or

half-scale state, depending on the MSB pin voltage. The VDD power

supply should have a smooth positive ramp without drooping to

have consistent results, especially in the region of VDD = 1.5 V to

2.3 V. The VSS supply has no effect on the power-on reset perform-

ance. The DAC register data stays at a zero-scale or half-scale

setting until a valid serial register data load takes place.

ESD PROTECTION CIRCUITS

All logic input pins contain back-biased ESD protection Zener

diodes that are connected to ground (DGND) and VDD, as

shown in Figure 25.

VDD

DIGITAL

INPUTS

Ω

DGND

Figure 25. Equivalent ESD Production Circuits

POWER SUPPLY SEQUENCE

As standard practice, it is recommended that VDD, VSS, and ground

be powered up prior to any reference. The ideal power-up sequence

is as follows: AGNDx, DGND, VDD, VSS, VREFx, and the digital inputs.

A noncompliance power-up sequence may elevate the reference

current, but the devices resume normal operation once VDD and

VSS are powered up.

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