M36LLR8760DF datasheet(4/19 Pages) STMICROELECTRONICS

4 / 19 page

M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1

4/19

SUMMARY DESCRIPTION

The

M36LLR8760T1,

M36LLR8760D1,

M36LLR8760M1 and M36LLR8760B1 combine

three memory devices in a Multi-Chip Package:

■

a 256-Mbit, Multiple Bank Flash memory, the

M30L0R8000(T/B)0 (Flash 1)

■

a 128-Mbit, Multiple Bank Flash memory, the

M58LR128GT/B (Flash 2)

■

a 64-Mbit PseudoSRAM, the M69KB096AA.

For detailed information on how to use the memo-

ry components, refer to the M30L0R8000(T/B)0,

M58LR128GT/B and M69KB096AA datasheets

which are available from your local STMicroelec-

tronics distributor and should be read in conjunc-

tion with the M36LLR8760x1 datasheet.

What

differs

between

the

M36LLR8760T1,

M36LLR8760D1 and M36LLR8760B1 is the con-

figuration of the two Flash memories:

■

in the M36LLR8760T1, Flash 1 and Flash 2

both have a Top Configuration (Parameter

Blocks located at the top of the address

space).

■

in the M36LLR8760D1, Flash 1 has a Bottom

Configuration (Parameter Blocks at the

bottom of the address space) and Flash 2 has

a Top Configuration.

■

In the M36LLR8760M1, Flash 1 has a Top

Configuration and Flash 2 has a Bottom

Configuration.

■

In the M36LLR8760B1, both Flash 1 and

Flash 2 have a Bottom Configuration.

Recommended operating conditions do not allow

more than one memory to be active at the same

time.

The memories are offered in a Stacked LFBGA88

(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-

age.

In addition to the standard version, the package is

also available in Lead-free version, in compliance

with JEDEC Std J-STD-020B, the ST ECOPACK

7191395 Specification, and the RoHS (Restriction

of Hazardous Substances) directive. All packages

are compliant with Lead-free soldering processes.

The memory is supplied with all the bits erased

(set to ‘1’).

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