MSM5416273 datasheet(39/40 Pages) OKI

39 / 40 page

¡ Semiconductor

MSM5416273

39/40

SAM Stop Set Cycle (CBRS): RAS falling edge --- CAS = "L", WE = "L", DSF = "H"

SAM stop location data (boundaries) are latched from address inputs at the falling edge of RAS.

To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored.

Once the CBRS is executed, the programmable SAM stop operation continues until CBRR.

SAM Stop Boundary Table

Number of Stop Points

Address

256

128

Size of Partition

A CBRR can reset the programmable SAM stop operation, and persistent mask write operation.

The CBRR will take effect immediately; it doesn’t require a split transfer cycle.

POWER UP

Power must be applied to the RAS and TRG input signals to pull them "high" before, or at the

same time as, the VCC supply is turned on. After power-up, a pause of 200 ms minimum is

required with RAS and TRG held "high". After the pause, a minimum of 8 RAS and 8 SC dummy

cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer

operations can begin. During the initialization period, the TRG signal must be held "high". If the

internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8

RAS cycles.

(NOTE) INITIAL STATE AFTER POWER UP

The initial state can not be guaranteed for various power up conditions and input signal levels.

Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non

Persistent Write-per-bit mode) after the initialization of the device is performed and before valid

operations begin.

MSM5416273 데이터시트(PDF) 39 Page - OKI electronic componets