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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STV0974E 데이터시트(PDF) 32 Page - STMicroelectronics |
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STV0974E 데이터시트(HTML) 32 Page - STMicroelectronics |
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32 / 69 page  32/61 STV0974 Functional description Timing constraints: Note: To be compatible with external power-on/internal power-down modes (ex: external VDD on and PDN low), all input pads from baseband side as well as SCL and SDA pads on both sensor and baseband sides are “fail-safe”. The “timing constraints” mentioned above correspond to the minimum delay needed between signals, in order to follow a correct power up sequence and insure an adequate initialization phase. Referring to the application schematics ( Section 8), STMicroelectronics recommends to connect POR pin (internal supply) to RST pin (Reset). Figure 20: Boot-up phase machine Table 21: Timing constraints Min. Max. Unit t1 0 ms t2 20 µs t3 20 clk cycles t4 2 ms t5 7 µs PDN RST Mode Reset Boot Clk VDD t1 t2 t5 Sleep POR t3 t4 |
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