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CY2292
Document #: 38-07449 Rev. *B
Page 8 of 11
t9A
Clock Jitter[14]
Peak-to-peak period jitter (t9A max. – t9A min.),
% of clock period (fOUT < 4 MHz)
< 0.5
1
%
t9B
Clock Jitter[14]
Peak-to-peak period jitter (t9B max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
< 0.7
1
ns
t9C
Clock Jitter[14]
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
< 400
500
ps
t9D
Clock Jitter[14]
Peak-to-peak period jitter
(fOUT > 50 MHz)
< 250
350
ps
t10A
Lock Time for
CPLL
Lock Time from Power-up
< 25
50
ms
t10B
Lock Time for
UPLL and SPLL
Lock Time from Power-up
< 0.25
1
ms
Slew Limits
CPU PLL Slew Limits
CY2292I
20
66.6
MHz
CY2292FI
20
60
MHz
Switching Waveforms
Switching Characteristics, Industrial 3.3V (continued)
Parameter
Name
Description
Min.
Typ.
Max.
Unit
All Outputs, Duty Cycle and Rise/Fall Time
t1
OUTPUT
t2
t3
t4
t5
OE
ALL
THREE-STATE
OUTPUTS
t6
Output Three-State Timing[4]
CLK Outputs Jitter and Skew
t7
CLK
OUTPUT
RELATED
CLK
t9A
CPU Frequency Change
SELECT
CPU
OLD SELECT
NEW SELECT STABLE
Fold
Fnew
t8 &t10
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