| 전자부품 데이터시트 검색엔진 |
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TE28F320B3BC90 데이터시트(PDF) 39 Page - Intel Corporation |
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TE28F320B3BC90 데이터시트(HTML) 39 Page - Intel Corporation |
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39 / 58 page ![]() 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 3UHOLPLQDU\ 33 5.0 Reset Operations 0580_09 NOTES: 1. If tPLPH is <100 ns the device may still RESET but this is not guaranteed 2. .Sampled, but not 100% tested. 3. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. Figure 9. AC Waveform: Deep Power-Down/Reset Operation IH V IL V RP# (P) PLPH t IH V IL V RP# (P) PLPH t (A) Reset during Read Mode Abort Complete PHQV t PHWL t PHEL t PHQV t PHWL t PHEL t (B) Reset during Program or Block Erase, < PLPH t PLRH t PLRH t IH V IL V RP# (P) PLPH t Abort Complete PHQV t PHWL t PHEL t PLRH t Deep Power- Down (C) Reset Program or Block Erase, > PLPH t PLRH t Reset Specifications Symbol Parameter Notes VCC = 2.7 V–3.6 V Unit Min Max tPLPH RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) 1,2 100 ns tPLRH RP# Low to Reset during Block Erase or Program 2,3 22 µs |
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