HT46R65 datasheet(13/48 Pages) HOLTEK

13 / 48 page

HT46R65/HT46C65

Rev. 1.80

July 14, 2005

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

There is another oscillator circuit designed for the real

time clock. In this case, only the 32.768kHz crystal oscil-

lator can be applied. The crystal should be connected

between OSC3 and OSC4.

The RTC oscillator circuit can be controlled to oscillate

quickly by setting the

²QOSC² bit (bit 4 of RTCC). It is

recommended to turn on the quick oscillating function

upon power on, and then turn it off after 2 seconds.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Although

the system enters the power down mode, the system

clock stops, and the WDT oscillator still works with a pe-

riod of approximately 65

ms at 5V. The WDT oscillator

can be disabled by options to conserve power.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock

(system clock/4) or a real time clock oscillator (RTC os-

cillator). The timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The WDT can be

disabled by options. But if the WDT is disabled, all exe-

cutions related to the WDT lead to no operation.

Once an internal WDT oscillator (RC oscillator with pe-

riod 65

ms at 5V normally) is selected, it is divided by

12~215 (by ROM code option to get the WDT time-out

period). The minimum period of WDT time-out period is

about 300ms~600ms. This time-out period may vary

with temperature, VDD and process variations. By se-

lection the WDT ROM code option, longer time-out peri-

ods can be realized. If the WDT time-out is selected 2

15,

the maximum time-out period is divided by 2

15~216about

2.1s~4.3s. If the WDT oscillator is disabled, the WDT

clock may still come from the instruction clock and oper-

ate in the same manner except that in the halt state the

WDT may stop counting and lose its protecting purpose.

In this situation the logic can only be restarted by exter-

nal logic. If the device operates in a noisy environment,

using the on-chip RC oscillator (WDT OSC) is strongly

recommended, since the HALT will stop the system

clock.

The WDT overflow under normal operation initializes a

²chip reset² and sets the status bit ²TO². In the HALT

mode, the overflow initializes a

²warm reset², and only

the program counter and SP are reset to zero. To clear

the contents of the WDT, there are three methods to be

adopted, i.e., external reset (a low level to RES), soft-

ware instruction, and a

²HALT² instruction. There are

two types of software instructions;

²CLR WDT² and the

other set

-²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one type of instruction can

be active at a time depending on the options

-²CLR

WDT

² times selection option. If the ²CLR WDT² is se-

lected (i.e., CLR WDT times equal one), any execution

of the

²CLR WDT² instruction clears the WDT. In the

case that

²CLR WDT1² and ²CLR WDT2² are chosen

(i.e., CLR WDT times equal two), these two instructions

have to be executed to clear the WDT; otherwise, the

WDT may reset the chip due to time-out.

Multi-function Timer

The HT46R65/HT46C65 provides a multi-function timer

for the WDT, time base and RTC but with different

time-out periods. The multi-function timer consists of an

8-stage divider and a 7-bit prescaler, with the clock

source coming from the WDT OSC or RTC OSC or the

instruction clock (i.e., system clock divided by 4). The

multi-function timer also provides a selectable fre-

quency signal (ranges from fS/2

2 to f

S/2

8) for LCD driver

circuits, and a selectable frequency signal (ranging from

fS/2

2 to f

S/2

9) for the buzzer output by options. It is rec-

ommended to select a nearly 4kHz signal for the LCD

driver circuits to have proper display.

Time Base

The time base offers a periodic time-out period to gener-

ate a regular internal interrupt. Its time-out period

ranges from 2

12/f

S to 2

15/f

S selected by options. If time

base time-out occurs, the related interrupt request flag

(TBF; bit 5 of INTC1) is set. But if the interrupt is en-

abled, and the stack is not full, a subroutine call to loca-

tion 14H occurs.

T i m e - o u t R e s e t

2 1 5 / f S ~ 2 1 6 / f S

2 1 4 / f S ~ 2 1 5 / f S

2 1 3 / f S ~ 2 1 4 / f S

2 1 2 / f S ~ 2 1 3 / f S

S y s t e m C l o c k / 4

D i v i d e r

W D T C l e a r

R O M

C o d e

O p t i o n

W D T

O S C 1 2 k H z

R T C

O S C 3 2 7 6 8 H z

C K T

f S

W D T

P r e s c a l e r

M a s k O p t i o n

f S / 2 8

Watchdog Timer

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