4256BWP datasheet(11/25 Pages) STMICROELECTRONICS

11 / 25 page

11/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

Figure 9. Read Mode Sequences

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

Read Operations

Read operations are performed independently of

the state of the Write Control (WC) signal.

After the successful completion of a Read opera-

tion, the device’s internal address counter is incre-

mented by one, to point to the next byte address.

Random Address Read

A dummy Write is first performed to load the ad-

dress into this address counter (as shown in Fig-

ure 9.) but

without sending a Stop condition. Then,

the bus master sends another Start condition, and

repeats the Device Select Code, with the RW bit

set to 1. The device acknowledges this, and out-

puts the contents of the addressed byte. The bus

master must

not acknowledge the byte, and termi-

nates the transfer with a Stop condition.

Current Address Read

For the Current Address Read operation, following

a Start condition, the bus master only sends a De-

vice Select Code with the R/W bit set to 1. The de-

vice acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The bus master ter-

minates the transfer with a Stop condition, as

shown in Figure 9.,

without acknowledging the

byte.

DEV SEL *

BYTE ADDR

DEV SEL

DATA OUT 1

AI01105C

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

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