CF52012 datasheet(40/48 Pages) INTEL

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Memory Array Organization on page 7

1.8. Power Mode

EPCQ devices support active and standby power modes. When the nCS signal is low,

the device is enabled and is in active power mode. The FPGA is configured while the

EPCQ device is in active power mode. When the nCS signal is high, the device is

disabled but remains in active power mode until all internal cycles are completed, such

as write or erase operations. The EPCQ device then goes into standby power mode.

The ICC1 and ICC0 parameters list the VCC supply current when the device is in active

and standby power modes.

1.9. Timing Information

Note:

The values in the following tables are finalized for EPCQ16, EPCQ32, EPCQ64,

EPCQ128, EPCQ256, and EPCQ512/A devices.

Related Information

Summary of Operation Codes on page 29

1.9.1. Write Operation Timing

Figure 22.

Write Operation Timing Diagram

DATA0

nCS

DCLK

DATA

tNCSH

tNCSSU

tDSU

tDH

tCL

tCH

tCSH

Bitn

Bitn- 1

Bit 0

High Impedance

Table 33.

Write Operation Parameters

Symbol

Parameter

Min

Typical

Max

Unit

fWCLK

Write clock frequency (from the FPGA,

download cable, or embedded processor) for

write enable, write disable, read status, read

device identification, write bytes, erase bulk,

and erase sector operations for all devices

except EPCQ512/A

—

108

MHz

Write clock frequency (from the FPGA,

download cable, or embedded processor) for

write enable, write disable, read status, read

device identification, write bytes, erase bulk,

and erase sector operations for EPCQ512/A

—

133

MHz

tCH (19)

DCLK

high time for all devices except

EPCQ512/A

—

continued...

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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