STC89LE52RC datasheet(11/165 Pages) STC

11 / 165 page

2.1.1 Idle Mode

An instruction that sets IDL/PCON.0 causes that to be the last instruction executed before going into the idle

mode, the internal clock is gated off to the CPU but not to the interrupt, timer, WDT and serial port functions. The

CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator,

and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle

was activated. ALE and PSEN hold at logic high levels. Idle mode leaves the peripherals running in order to allow

them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, Timer 2 and UART will continue to

function during Idle mode.

There are two ways to terminate the idle. Activation of any enabled interrupt will cause IDL/PCON.0 to be

cleared by hardware, terminating the idle mode. The interrupt will be serviced, and following RETI, the next

instruction to be executed will be the one following the instruction that put the device into idle.

The flag bits (GFO and GF1) can be used to give art indication if an interrupt occurred during normal operation

or during Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is

terminated by an interrupt, the interrupt service routine can examine the flag bits.

The other way to wake-up from idle is to pull RESET high to generate internal hardware reset.Since the clock

oscillator is still running, the hardware reset neeeds to be held active for only two system clock cycles(24 system

clock) to complete the reset.

2.1 Power Management

There are two power saving modes, which are selectable to drive the STC89xx enter power-saving mode by set-

ting the following SFR PCON.

PCON register (Power Control Register)

LSB

bit

B5B4B3B2B1B0

name

SMOD SMOD0

POF

GF1

GF0

IDL

SMOD : Double baud rate of UART interface

Keep normal baud rate when the UART is used in mode 1,2 or 3. (defaut)

Double baud rate bit when the UART is used in mode 1,2 or 3.

SMOD0 : SM0/FE bit select for SCON.7; setting this bit will set SCON.7 as Frame Error function. Clearing it to

set SCON.7 as one bit of UART mode selection bits.

: Reserved

POF

: Power-On flag. It is set by power-off-on action and can only cleared by software.

GF1

: General-purposed flag 1

GF0

: General-purposed flag 0

: Power-Down bit.

IDL

: Idle mode bit.

Chapter 2 POWER MANAGENMENT, RESET

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