PD780C datasheet(10/24 Pages) NEC

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Timing Waveforms (cont)

Interrupt Reques t/Acknowledge Cycle

Last

M Cycle

ofInstruction

LastTState

Ao-A15

WAIT

- ---,- - --- ----

----1

- --

------

�--�'------

:: :::

Input and Output Cycles

In 110 operations, a single wait state (Tw) is automat

ically included to provide adequate time for an 110 port

to decode the address from the port address lines and

initiate a wait condition if needed.

Opcode Fetch Instruction Cycle

At the beginning of the cycle, the contents of the pro

gram counter are placed on the address bus. After ap

proximately one-half cycle, MREQ is asserted and its

falling edge can be used directly by the external mem

ory as a chip enable signal. The data from the exter

nal memory can be gated onto the data bus when RD

is asserted. The CPU reads the data at the rising edge

of T3' During T3 and T4, external dynamic memory is

refreshed while the instruction is decoded and exe

cuted. The assertion of RFSH indicates that the ex

ternal dynamic memory requires a refresh read.

4-12

Memory Read or Write Cycles

In read and write operations, the MREQ and RD

signals function the same as they do in opcode fetch

operations. In a write operation MREQis asserted and

can be used directly by external memory as a chip

enable signal when information on the address bus

is stable. The WR signal is used as a write strobe to

almost any type of semiconductor memory, and is

asserted when data on the data bus is stable.

Interrupt Request/Acknowledge Cycle

The interrupt signal is sampled at the rising edge of

the final clock pulse at the end of an instruction.

When an interrupt is accepted, an Ml cycle is begun.

Instead of MREQ, 10RQis asserted during this cycle

to indicate that an 8-bit vector address can be placed

on the data bus by the interrupting device. This cycle

includes the automatic addition of two wait states to

facilitate the implementation of a daisy-chain priori

ty interrupt protocol.

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