NT5CB256M8FN datasheet(46/163 Pages) NANYA

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DDR3(L) 2Gb SDRAM

NT5CB(C)256M8FN / NT5CB(C)128M16FP

Version 1.7

Nanya Technology Cooperation ©

04/2015

MPR MR3 Register Definition

MR3 A[2]

MR3 A[1:0]

Function

don't care

(0 or 1)

Normal operation, no MPR transaction.

All subsequent Reads will come from DRAM array.

All subsequent Writes will go to DRAM array.

See the following table

Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].

MPR Functional Description



One bit wide logical interface via all DQ pins during READ operation.



DQ [0] drives information from MPR.



DQ [7:1] either drive the same information as DQ [0], or they drive 0.



Addressing during for Multi Purpose Register reads for all MPR agents:



BA [2:0]: don’t care.



A [1:0]: A [1:0] must be equal to “00”. Data read burst order in nibble is fixed.



A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is

switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *)



A [9:3]: don’t care.



A10/AP: don’t care.



A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0



A11, A13: don’t care.



Regular interface functionality during register reads:



Support two Burst Ordering which are switched with A2 and A[1:0]=00.



Support of read burst chop (MRS and on-the-fly via A12/BC).



All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the

DDR3(L) SDRAM.



Regular read latencies and AC timings apply.



DLL must be locked prior to MPR READs.

Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

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