ADP3419 datasheet(3/16 Pages) AD

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ADP3419

Rev. A | Page 3 of 16

SPECIFICATIONS

VCC = SD = 5 V, BST = 4 V to 26 V, TA = 0°C to 100°C, unless otherwise noted.

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)

Input Voltage High

VIH

2.0

Input Voltage Low

VIL

0.8

Input Current

IIN

Inputs = 0 V or 5 V

−1

µA

DRVLSD Propagation Delay Time

tpdl

DRVLSD,

tpdh

DRVLSD

CLOAD = 3 nF, Figure 3

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current

BST − SW = 4.6 V

1.7

3.3

Ω

Output Resistance, Sinking Current

BST − SW = 4.6 V

0.8

2.3

Ω

Transition Times

trDRVH

BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4

tfDRVH

BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4

Propagation Delay Times1

tpdhDRVH

BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4

tpdlDRVH

BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4

LOW-SIDE DRIVER

Output Resistance, Sourcing Current

1.7

3.3

Ω

Output Resistance, Sinking Current

0.8

2.3

Ω

Transition Times

trDRVL

CLOAD = 3 nF, Figure 4

tfDRVL

CLOAD = 3 nF, Figure 4

Propagation Delay Times1, 2

tpdhDRVL

CLOAD = 3 nF, Figure 4

tpdlDRVL

CLOAD = 3 nF, Figure 4

SW Transition Timeout2

tSWTO

BST − SW = 4.6 V

150

350

600

Zero-Crossing Threshold

VZC

SUPPLY

Supply Voltage Range

VCC

4.6

Supply Current

Normal Mode

ISYS(NM)

ICC + IBST, IN = 0 V or 5 V

0.8

1.5

Shutdown Mode

ISYS(SD)

ICC + IBST, SD = 0 V

325

600

µA

Undervoltage Lockout Threshold

VCC rising

3.8

4.25

4.5

Undervoltage Lockout Hysteresis3

VCC falling

120

1 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%.

2 The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO.

3 Guaranteed by characterization, not production tested.

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