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BK2425WD 데이터시트(PDF) 19 Page - List of Unclassifed Manufacturers

부품명 BK2425WD
상세설명  Low Power High Performance 2.4 GHz GFSK Transceiver
PDF  30 Pages
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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Logo ETC2 - List of Unclassifed Manufacturers

BK2425WD 데이터시트(HTML) 19 Page - List of Unclassifed Manufacturers

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BK2425
Revision 1.0
Proprietary and Confidential
Page 19 of 30
17
FIFO_STATUS
FIFO Status Register
Reserved
7
0
R/W
Only '0' allowed
TX_REUSE
6
0
R
Reuse last transmitted data packet if set
high.
The packet is repeatedly retransmitted as
long as CE is high. TX_REUSE is set by
the SPI command REUSE_TX_PL, and is
reset by the SPI command
W_TX_PAYLOAD or FLUSH TX
TX_FULL
5
0
R
TX FIFO full flag
1: TX FIFO full; 0: Available locations in
TX FIFO
TX_EMPTY
4
1
R
TX FIFO empty flag.
1: TX FIFO empty
0: Data in TX FIFO
Reserved
3:2
00
R/W
Only '00' allowed
RX_FULL
1
0
R
RX FIFO full flag
1: RX FIFO full
0: Available locations in RX FIFO
RX_EMPTY
0
1
R
RX FIFO empty flag
1: RX FIFO empty
0: Data in RX FIFO
N/A
ACK_PLD
255:0
X
W
Written by separate SPI command ACK
packet payload to data pipe number PPP
given in SPI command
Used in RX mode only
Maximum three ACK packet payloads can
be pending. Payloads with same PPP are
handled first in first out.
N/A
TX_PLD
255:0
X
W
Written by separate SPI command TX data
pay-load register 1 - 32 bytes. This register
is implemented as a FIFO with three
levels.
Used in TX mode only
N/A
RX_PLD
255:0
X
R
Read by separate SPI command
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO
with three levels.
All RX channels share the same FIFO.
1C
DYNPD
Enable dynamic payload length
Reserved
7:6
0
R/W
Only ‘00’ allowed
DPL_P5
5
0
R/W
Enable dynamic payload length data pipe
5.
(Requires EN_DPL and ENAA_P5)
DPL_P4
4
0
R/W
Enable dynamic payload length data pipe
4.
(Requires EN_DPL and ENAA_P4)
DPL_P3
3
0
R/W
Enable dynamic payload length data pipe
3.
(Requires EN_DPL and ENAA_P3)
DPL_P2
2
0
R/W
Enable dynamic payload length data pipe
2.
(Requires EN_DPL and ENAA_P2)
DPL_P1
1
0
R/W
Enable dynamic payload length data pipe
1.
(Requires EN_DPL and ENAA_P1)
DPL_P0
0
0
R/W
Enable dynamic payload length data pipe
0.



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