전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

TM7708 데이터시트(PDF) 10 Page - Shenzhen Titan Micro Electronics Co., Ltd.

부품명 TM7708
상세설명  Two-bIt digital analog converter
PDF  46 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TITAN [Shenzhen Titan Micro Electronics Co., Ltd.]
홈페이지  http://www.titanmec.com/index.php/en/
Logo TITAN - Shenzhen Titan Micro Electronics Co., Ltd.

TM7708 데이터시트(HTML) 10 Page - Shenzhen Titan Micro Electronics Co., Ltd.

Back Button TM7708 Datasheet HTML 6Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 7Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 8Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 9Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 10Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 11Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 12Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 13Page - Shenzhen Titan Micro Electronics Co., Ltd. TM7708 Datasheet HTML 14Page - Shenzhen Titan Micro Electronics Co., Ltd. Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 46 page
background image
©
Titan Micro Electronics
V1.1
www.titanmec.com
-10-
24 bit 模数转换器 TM7707/8
为
25Hz 或 50Hz ）。60Hz 时，PSRR 超过 120dB （滤波器陷波为 20Hz 或 60Hz ）。
19. PSRR 由增益和 VDD 决定，如下：
增益
1
2
4
8~128
VDD=3V
86
78
85
93
VDD=5V
90
78
84
91
八、定时参数
（
VDD= +2.7V~+5.2V；GND=0V；fCLKIN =2.4567MHz；Input Logic 0=0 V，
Logic 1 = VDD 除非另有说明）
Parameter
Limit at
TMIN ,TMAX
(B Version)
Units
Conditions/Comments
fCLKIN
3,4
400
kHzmin
Master Clock Frequency: Crystal
Oscillator or Externally Supplied
2.5
MHz max
for Specified Performance
tCLKIN LO
0.4×tCLKIN
ns min
Master Clock Input Low Time.
tCLKIN=1/ fCLKIN
tCLKIN HI
0.4×tCLKIN
ns min
Master Clock Input High Time.
t1
500×tCLKIN
ns mon
DRDY High Time
t2
100
ns min
RESETPulsewidth
Read Operation
t3
0
ns min
DRDY to CS Setup Time
t4
120
ns min
CS Falling Edge to SCLK Rising
Edge Setup Time
t5
5
0
ns min
SCLK Falling Edge to Data Valid
Delay
80
ns max
VDD=+5V
100
ns max
VDD=+3.0V
t6
100
ns min
SCLK High Pulsewidth
t7
100
ns min
SCLK Low Pulsewidth
t8
0
ns min
CS Rising Edge to SCLK Rising
Edge Hold Time
t9
6
10
ns min
Bus RelinguishTimeafter SCLK
Rising Edge
60
ns max
VDD=+5V
100
ns max
VDD=+3.0V
t10
100
ns max
SCLK Falling Edge to DRDY High7
Write Operation
t11
120
ns min
CS Falling Edge to SCLK Rising
Edge Setup Time
t12
30
ns min
Data Valid to SCLK Rising Edge



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com