2013/05/13

A.1

10

EM8635

Functional Description

UVLO

An UVLO comparator is implemented in EM8635 to

monitor the VDD pin voltage. As shown in Fig. 14, a

hysteresis is built in to prevent the shutdown from

the voltage drop during startup. The UVLO (on) and

UVLO

(off)

are

setting

at

15V

and

8.5V,

respectively.

Fig. 14

Startup Operation

Fig. 15 shows a typical startup circuit and

transformer auxiliary winding for the EM8635

application, it consumes only startup current

(typical 6uA) and the current supplied through the

When VDD reaches UVLO (on) voltage, EM8635

begins switching and

the current consumed

increases to 2.5mA. Then, the power required is

supplied from the transformer auxiliary winding.

The hysteresis of UVLO (off) provides more holdup

time, which allows using a small capacitor for VDD.

The ultra low startup current (typical 6uA) allow

provides a fast startup and low power dissipation

solution.

Fig. 15

Switching Frequency

To guarantee accurate frequency, EM8635 is

trimmed to 7% tolerance. The switching frequency

is 65KHz (Tpy.) with +-6% jitter range. The internal

oscillator also generates slope compensation, 75%

maximum duty limit.

Leading Edge Blanking (LEB)

Each time the power MOSFET turn on, the MOSFET

and gate driver sourcing current comprise the

current spike. To avoid premature termination of

the switching pulse, a leading edge blanking time is

built in. During the blanking time (300nS), the

PWM comparator is off and cannot switch off the

gate driver. It is recommended to adopt a smaller

R-C filter (as show ad Fig.16) for high power

application to avoid the total spike width over

300nS leading edge blanking time.

Fig. 16

VDD

t

t

Start up Current(6uA)

Operation Current (2.5mA)

UVLO (on)

UVLO(off)

EM8635

AC

INPUT

BNO

COMP

GND

CS

GATE

VDD

Rstart

EM8635

GND

CS

GATE

VDD

300nS LEB