RFM219SW

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> 0.5 SCL cycle

> 0.5 SCL cycle

CSB

FCSB

SCL

SDA

X

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

X

r/w = 1

register address

register read data

Figure 13. SPI Read Register Timing

> 0.5 SCL cycle

> 0.5 SCL cycle

CSB

FCSB

SCL

SDA

X

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

X

r/w = 0

register address

register write data

Figure 14. SPI Write Register Timing

5.6.2 FIFO Read Operation

When reading the 32-byte FIFO, the internal read pointer will automatically increment after each byte is read out. The MCU must

pull the FCSB to low for at least 1 SCL cycle before issuing the first rising edge of SCL. After issuing the last falling edge of SCL,

the MCU must wait for at least 2 us before pulling the FCSB back to high. Furthermore, the MCU must pull up the FCSB for at

least 4 us before reading the next byte of the FIFO. It allows the internal circuit to generate the FIFO interrupts according to the

current status.

> 1 SCL cycle

> 2 us

> 4 us

> 1 SCL cycle

> 2 us

CSB

FCSB

SCL

SDA

X

7

6

5

4

3

2

1

0

X

7

6

5

4

3

2

1

0

X

FIFO read data

FIFO read data

Figure 15. SPI Read FIFO Timing