MSM80C85AHJS datasheet(15/29 Pages) OKI

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¡ Semiconductor

MSM80C85AHRS/GS/JS

Notes: (1) A8 - A15 address Specs apply to IO/M, S0 and S1.

(2) Test condition: tCYC=200 ns CL=150 pF

(3) For all output timing where CL=150 pF use the following correction factors:

25 pF £ CL < 150 pF : –0.10ns/pF

150 pF < CL £ 200 pF : +0.30ns/pF

(4) Output timings are measured with purely capacitive load.

(5) All timings are measured to output voltage VL=0.8 V, VH=2.2 V, and 1.5 V

with 10 ns rise and fall time on inputs.

(6) To calculate timing specifications at other values of tCYC use Table 7.

(7) Data hold time is guaranteed under all loading conditions.

2.4

Test Points

2.2

0.8

0.45

Input Waveform for A.C. Tests:

(1/2)T - 50

tAL

Min

(Ta = -40°C - +85°C, VCC = 4.5 V - 5.5 V, CL = 150 pF)

(1/2)T - 50

tLA

Min

(1/2)T - 20

tLL

Min

(1/2)T - 50

tLCK

Min

(1/2)T - 40

tLC

Min

(5/2+N)T - 150

tAD

Max

(3/2+N)T - 150

tRD

Max

(1/2)T - 10

tRAE

Min

(1/2)T - 40

tCA

Min

(3/2+N)T -70

tDW

Min

(1/2)T - 40

tWD

Min

(3/2+N)T - 70

tCC

Min

(1/2)T - 75

tCL

Min

(3/2)T - 200

tARY

Max

(1/2)T - 60

tHACK

Min

(1/2)T + 50

tHABF

Max

(1/2)T + 50

(2/2)T - 85

tHABE

Max

tAC

Min

(1/2)T - 60

Min

(1/2)T - 30

Min

(3/2)T - 80

tRV

Min

tLDR

Max

—

MSM80C85AH

Table 7 Bus Timing Specification as a TCYC Dependent

Note: N is equal to the total WAIT states.

T = tCYC

(2+N)T -130

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