MPC7455 datasheet(30/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 12 shows the L3 bus timing diagrams for the MPC7455 interfaced to PB2 or late write SRAMs.

Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs

5.2.5

IEEE 1149.1 AC Timing Specifications

Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through Figure 17.

Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) 1

At recommended operating conditions. See Table 4.

Parameter

Symbol

Min

Max

Unit

Notes

TCK frequency of operation

fTCLK

33.3

MHz

TCK cycle time

t TCLK

—

TCK clock pulse width measured at 1.4 V

tJHJL

—

TCK rise and fall times

tJR and tJF

TRST assert time

tTRST

—

Input setup times:

Boundary-scan data

TMS, TDI

tDVJH

tIVJH

—

Input hold times:

Boundary-scan data

TMS, TDI

tDXJH

tIXJH

—

L3_ECHO_CLK[0,2]

L3 Data and Data

VM = Midpoint Voltage (GVDD/2)

tL3DVEH

tL3DXEH

Parity Inputs

L3_CLK[0,1]

ADDR, L3_CNTL

tL3CHOV

tL3CHOX

L3DATA WRITE

tL3CHDZ

Outputs

Inputs

L3_ECHO_CLK[1,3]

tL3CHDV

tL3CHDX

tL3CHOZ

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