MSM82C59A-2JS datasheet(12/28 Pages) OKI

12 / 28 page

12/28

¡ Semiconductor

MSM82C59A-2RS/GS/JS

Contents of the Second Interrupt vector byte

The higher address of the interrupt service routine programmed by the second bytes (A8 -

A15) of the initialization sequence is released to the data bus.

A15

A14

A13

A12

A11

A10

Contents of the Third Interrupt Vector Byte

86 Mode (MSM80C86A-10/88A-10)

Apart from the two interrupt acknowledge cycles and the absence of a CALL operation

code, the 86 mode is the same as the 85 mode. The first INTA cycle freezes interrupt status

to resolve the priority internally in the same way as in 85 mode. When the device is used

as a master, an interrupt code is issued to the cascade line at the end of the INTA pulse.

During this first cycle, the data bus buffer is kept at high impedance without any data to

the CPU. During the second INTA cycle, the MSM82C59A-2 sends a byte of interrupt code

to the CPU. Note that in 86 mode, the Address Interval (ADI) control status is ignored and

A5-A10 is not used.

Interval = 4

7A7

111

110

101

100

011

010

001

000

Interval = 8

7A7

110

100

010

000

110

100

010

000

MSM82C59A-2JS 데이터시트(PDF) 12 Page - OKI electronic componets

MSM82C59A-2JS 데이터시트(HTML) 12 Page - OKI electronic componets

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

데이터시트 다운로드

링크 URL