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¡ Semiconductor

MSM82C84A-2RS/GS/JS

EXAMPLE OF USE (CSYNC)

The MSM82C84A-2 1/3 frequency divider counter is unsettled when the power is switched

on. Therefore, the CSYNC pin has been included to synchronize CLK with another signal.

When CSYNC is at high level, both CLK and PCLK are high-level outputs. If CSYNC is then

switched to low level, CLK is output from the next input clock rising edge, and is divided

by 3.

If CSYNC has not been synchronized with the input clock, use the following circuit to

achieve the required synchronization

External Sychronizing

Signal



D

CK≠

Q

D

CKØ

Q

EFI

CLK

CLK

CSYNC

MSM

82C84A-2

External Clock

Signal (EFI)

When an external clock EFI is used as the clock source

External Sychronizing

Signal

D

CK≠

Q

D

CKØ

Q

OSC

CLK

F/C

CSYNC

MSM

82C84A-2

When the crystal oscillator is used as the clock source

CLK

NOTES ON USE

The MSM82C84A-2 cannot be used if the MSM80C86A-10 or MSM80C88A-10 is used within the

range of 8 MHz < operating frequency £ 10 MHz.