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M440T1MV

Figure 13. Clock WRITE Mode AC Waveforms, Chip Enable-Controlled

Note: Clock Output Enable (GC) = High

Table 5. Memory/Clock WRITE Mode AC Characteristics

3. If E1 - E4 and EC goes low simultaneously with W1 - W4 and WC going low, the outputs remain in the high impedance state.

Symbol

M440T1MV

Unit

Memory

Clock

–85

–15

Min

Max

Min

Max

WRITE Cycle Time

85

150

ns

Address Valid to WRITE Enable Low

0

0

ns

Address Valid to Chip Enable Low

0

0

ns

WRITE Enable Pulse Width

60

100

ns

Chip Enable Low to Chip Enable High

65

150

ns

WRITE Enable High to Address Transition

0

10

ns

Chip Enable High to Address Transition

15

10

ns

Input Valid to WRITE Enable High

35

50

ns

Input Valid to Chip Enable High

35

50

ns

WRITE Enable High to Input Transition

0

0

ns

Chip Enable High to Input Transition

15

0

ns

(2,3)

WRITE Enable Low to Output Hi-Z

30

50

ns

Address Valid to WRITE Enable High

70

150

ns

Address Valid to Chip Enable High

70

150

ns

(3)

WRITE Enable High to Output Transition

5

5

ns

AI04652

tAVAV

tEHAX

tDVWH

A0-A5

EC

WC

DQC0-DQC7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tWHDX

DATA INPUT