54HC112 datasheet(5/6 Pages) SS

5 / 6 page

AC Electrical Characteristics5

High Speed CMOS Logic – 54HC112

Rev 1.0

24/11/17

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

2.0V

165

205

250

4.5V

Maximum Propagation

Delay,

CL = 50pF,

tr = tf = 6ns

Set to Q or Q

(Figure 2,4)

tPLH, tPHL

6.0V

2.0V

110

4.5V

Maximum Output

Transition time,

Any output

(Figure 1,4)

tTLH, tTHL

6.0V

CL = 50pF,

tr = tf = 6ns

Maximum Input

Capacitance

CIN

TYPICAL

Power Dissipation

Capacitance

(Per Flip-Flop)

CPD

4. -55˚C ≤ TJ ≤ +125˚C

5. Not production tested in die form, characterized by chip design and tested in package.

6. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

LIMITS

Timing Requirements5

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

2.0V

100

125

150

4.5V

Maximum Setup Time,

J or K to Clock

(Figure 3)

tSU

6.0V

CL = 50pF,

tr = tf = 6ns

2.0V

4.5V

Minimum Hold Time,

Clock to J or K

(Figure 3)

6.0V

CL = 50pF,

tr = tf = 6ns

2.0V

100

125

150

4.5V

Minimum Recovery

Time, Set or Reset

Inactive to Clock

(Figure 2)

CL = 50pF,

tr = tf = 6ns

trec

6.0V

2.0V

100

120

4.5V

Minimum Pulse Width,

Clock

(Figure 1)

6.0V

CL = 50pF,

tr = tf = 6ns

2.0V

100

120

4.5V

Minimum Pulse Width,

Set or Reset

(Figure 2)

6.0V

CL = 50pF,

tr = tf = 6ns

2.0V

1000

4.5V

500

Maximum Input Rise

and Fall times

(Figure 1)

tr, tf

6.0V

CL = 50pF,

tr = tf = 6ns

400

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