Rev 1.0

07/02/19

Quad 2-Input NAND Gates in bare die form

High Speed CMOS Logic – 74HC00

 

Description

Features:

 

Output Drive Capability: 10 LSTTL Loads

 

 

 

 

 

54HC00 provides x4 independent 2-input NAND gates

performing the Boolean function Y = A • B or Y = A + B.

The device is fabricated using a 2.5µm 5V CMOS process

combining high speed LSTTL performance with CMOS low

power. Internal circuitry comprises of 3 stages and includes

buffered output for high noise immunity and stability.

Device inputs are compatible with standard CMOS outputs;

with pull-up resistors, they are compatible with LSTTL

outputs. All inputs are equipped with protection circuits

against static discharge and transient excess voltage.

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

Function compatible with 54LS00

High Noise Immunity CMOS process.

 

 

Ordering Information

Die Dimensions in µm (mils)

The following part suffixes apply:

610 (24)

 

No suffix - MIL-STD-883 /2010B Visual Inspection

 

 

 

For High Reliability versions of this product please see

 

54HC00

 

 

 

 

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Die Size (Unsawn)

610 x 610

24 x 24

µm

mils

Minimum Bond Pad Size

85 x 85

3.35 x 3.35

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

 

Sawn Wafer on Tape – On request

 

Unsawn Wafer – On request

 

Die Thickness <> 350µm(14 Mils) – On request

 

Assembled into Ceramic Package – On request

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