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DUT

OUTPUT

TEST POINT

* Includes all probe and jig capacitance

Figure 5 – Data Transition Timing, Serial Input & Clock

Switching Waveforms continued

Figure 7 – Test Setup

High Speed CMOS Logic – 54HC595

Rev 1.0

05/02/19

Figure 3 – Clock Propagation Delay & Output Timing

Figure 4 – Enable to Output Propagation Delay

Figure 6 – Shift Clock to Register Clock Setup Timing

TESTING

CONNECT TO GND WHEN

TESTING

DUT

OUTPUT

TEST POINT

* Includes all probe and jig capacitance

1KΩ

Figure 8 – Test Setup