HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series

Rev.3.00, Feb.02.2004, page 10 of 26

Write Cycle 2 (4.5

≤ V

CC

≤ 5.5 V)

Parameter

Symbol

Min*

3

Typ

Max

Unit

Test conditions

Address setup time

0





ns

Address hold time

50





ns

CE to write setup time (WE controlled)

0





ns

CE hold time (WE controlled)

0





ns

WE to write setup time (CE controlled)

0





ns

WE hold time (CE controlled)

0





ns

OE to write setup time

0





ns

OE hold time

0





ns

Data setup time

50





ns

Data hold time

0





ns

WE pulse width (WE controlled)

100





ns

CE pulse width (CE controlled)

100





ns

Data latch time

50





ns

Byte load cycle

0.2



30

µs

Byte load window

100





µs

Write cycle time





10*

4

ms

Time to device busy

120





ns

Write start time

0*

5





ns

Reset protect time*

2

100





µs

Reset high time*

2, 6

1





µs

are no longer driven.

2. This function is supported by only the HN58V66A.

3. Use this device in longer cycle than this value.

automatically completes the internal write operation within this value.

6. This parameter is sampled and not 100% tested.

7. A6 through A12 are page address and these addresses are latched at the first falling edge of

WE.

8. A6 through A12 are page address and these addresses are latched at the first falling edge of

CE.

9. See AC read characteristics.