전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

DLP2000AFQC 데이터시트(PDF) 7 Page - Texas Instruments

Click here to check the latest version.
부품명 DLP2000AFQC
상세설명  DLP2000 (.2 nHD) DMD
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

DLP2000AFQC 데이터시트(HTML) 7 Page - Texas Instruments

Back Button DLP2000AFQC Datasheet HTML 3Page - Texas Instruments DLP2000AFQC Datasheet HTML 4Page - Texas Instruments DLP2000AFQC Datasheet HTML 5Page - Texas Instruments DLP2000AFQC Datasheet HTML 6Page - Texas Instruments DLP2000AFQC Datasheet HTML 7Page - Texas Instruments DLP2000AFQC Datasheet HTML 8Page - Texas Instruments DLP2000AFQC Datasheet HTML 9Page - Texas Instruments DLP2000AFQC Datasheet HTML 10Page - Texas Instruments DLP2000AFQC Datasheet HTML 11Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 40 page
background image
7
DLP2000
www.ti.com
DLPS140 – APRIL 2019
Product Folder Links: DLP2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to GND (VSS). VOFFSET, VCC, VBIAS, VRESET and VSS power supplies are required for the normal DMD
operating mode.
(3)
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than 8.75 V.
(4)
BSA to Reset Timing specifications are synchronous and guaranteed for DCLK between 60 MHz and 80 MHz.
(5)
The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation) or of any point along the
Window Edge as defined in Figure 10.
(6)
The DLP2000 DMD is intended for use in well controlled, low dew point environments. Please contact your local TI sales person or TI
distributor representative to determine if this device is suitable for your application and operating environment compared to other DMD
solutions. DLP® Products offers a broad portfolio of DMDs suitable for a wide variety of applications.
(7)
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 10.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply Voltage
VCC
LVCMOS Logic Supply Voltage (2)
–0.5
4
V
VOFFSET
Mirror Electrode and HVCMOS Voltage (2)
–0.5
8.75
V
VBIAS
Mirror Electrode Voltage
–0.5
17
V
|VBIAS – VOFFSET|
Supply Voltage Delta (3)
8.75
V
VRESET
Mirror Electrode Voltage
–11
0.5
V
Input Voltage
Input voltage: other inputs
See (2)
–0.5
VCC + 0.3
V
Clock Frequency
DCLK
Clock Frequency (4)
60
80
MHz
Environmental
TARRAY and TWINDOW
Temperature – operational (5)
–20
90
°C
Temperature – non-operational(5)
–40
90
°C
TDP
Dew Point Temperature - operating and
non-operating (non-condensing)
See Note(6)
°C
|TDELTA|
Absolute Temperature delta between any
point on the window edge and the ceramic
test point TP1(7)
30
°C
(1)
The DLP2000 DMD is intended for use in well controlled, low dew point environments. Please contact your local TI sales person or TI
distributor representative to determine if this device is suitable for your application and operating environment compared to other DMD
solutions. DLP Products offers a broad portfolio of DMDs suitable for a wide variety of applications.
6.2 Storage Conditions
Applicable before the DMD is installed in the final product
MIN
MAX
UNIT
TDMD
DMD Temperature
–40
85
°C
TDP
Dew Point Temperature
(non-condensing)
See Note(1)
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com