PSD813F1 datasheet(12/110 Pages) STMICROELECTRONICS

12 / 110 page

PSD813F1

12/110

Note: 1. The pin numbers in this table are for the PLCC package only. See the Figure 2., page 7, for pin numbers on other package type.

2. These functions can be multiplexed with other functions.

PC5

I/O

PC5 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC5) output.

3. Input to the PLDs.

4. TDI input2 for the JTAG Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6

I/O

PC6 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC6) output.

3. Input to the PLDs.

4. TDO output2 for the JTAG Interface.

This pin can be configured as a CMOS or Open Drain output.

PC7

I/O

PC7 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC7) output.

3. Input to the PLDs.

4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

PD0

I/O

PD0 pin of Port D. This port pin can be configured to have the following functions:

1. ALE/AS input latches address output from the MCU.

2. MCU I/O – write or read from a standard output or input port.

3. Input to the PLDs.

4. CPLD output (External Chip Select).

PD1

I/O

PD1 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and

the CPLD AND Array.

PD2

I/O

PD2 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/

O. When High, the PSD memory blocks are disabled to conserve power.

VCC

15, 38

Supply Voltage

GND

1, 16,

Ground pins

Pin Name

Type

Description(1)

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