NM14F2KSLAXCL-3BNA datasheet(35/121 Pages) NANYA

35 / 121 page

Version 1.6

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 2Gb LPDDR2

NM148(F)2KSLAXCL/NM1482NSLAXCL

NTC Proprietary

Level: Property

Multi Page Program with Data Cache

The device has a Multi Page Program with Data Cache operation, which enables even higher speed program

operation compared to Auto Page Program with Data Cache as shown below. When the block address

changes (increments) this sequenced has to be started from the beginning.

The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)

For X8 :

For X16 :

After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details

of Auto Program with Data Ca

che, refer to “Auto Page Program with Data Cache”.

The data is transferred (programmed) from the page buffer to the selected page on the rising edge of

 following input of the “15h” or

“10h” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If

the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum

loop number set in the device is reached.

NM14F2KSLAXCL-3BNA 데이터시트(PDF) 35 Page - Nanya Technology Corporation.