VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6464

64x64 Crosspoint Switch

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

G52219-0, Rev. 2.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

8/4/98

Figure 3 VSC6464 Asynchronous Timing Diagram

Table 3: VSC6464 Asynchronous Timing Table

Note: 1.) Duty cycle distortion = (duty cycle in - duty cyle out)/duty cycle in * 100%, measured with a 2ns pulse width.

Figure 4 VSC6464 Synchronous Data Input Timing Diagram

Table 4: VSC6464 Synchronous Data Input Timing Table

Parameters

Description

Min

Typ

Max

Units

Minimum DIN<63:0> pulse width, 50% input

1.25

-

-

ns

DIN<63:0> to DOUT<63:0> propagation delay

-

-

6.5

ns

DIN<63:0> to DOUT<63:0> propagation delay

2.2

-

-

ns

DOUT<63:0> asynchronous mode data skew (any input

to any output, add 0.1 for SSO)

-

-

1.4

ns

DOUT<63:0> asynchronous mode data skew (broadcast,

add 0.1 for SSO)

-

-

0.75

ns

-

-

-

25

%

Parameters

Description

Min

Typ

Max

Units

Maximum CKI frequency, 50% input

-

-

250

MHz

DIN<63:0> data setup time with respect to CKI

0.5

-

-

ns

DIN<63:0> data hold time with respect to CKI

0.4

-

-

ns

DOUT<63:0>

DIN<63:0>

TASKW

TAMX

TPW

TAMN

TINSU TINH

DIN<63:0>

CKI