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MSHFS 데이터시트(PDF) 3 Page - Mixed Signal Integration

부품명 MSHFS
상세설명  Selectable High Frequency LP/BP Filter
PDF  5 Pages
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제조업체  MSI [Mixed Signal Integration]
홈페이지  https://www.mix-sig.com
Logo MSI - Mixed Signal Integration

MSHFS 데이터시트(HTML) 3 Page - Mixed Signal Integration

  MSHFS Datasheet HTML 1Page - Mixed Signal Integration MSHFS Datasheet HTML 2Page - Mixed Signal Integration MSHFS Datasheet HTML 3Page - Mixed Signal Integration MSHFS Datasheet HTML 4Page - Mixed Signal Integration MSHFS Datasheet HTML 5Page - Mixed Signal Integration  
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TYPE
Lowpass
Bandpass
0
Butterworth
Full Octave
1
Bessel
Third Octave
2
Elliptic
Sixth Octave
The filter type is selected using the two filter se-
lect pins, TYPE and FSEL, FSEL is a CMOS level
pin that selects lowpass or bandpass (lowpass
= 0, bandpass = 1). TYPE Is a tertiary control pin
that selects the filter response. State 0 is VSS,
state 1 is GND and state 2 is VDD.
Selectable High Frequency LP/BP Filter
Data Sheet
7/2016
Pin Description________________
1. TYPE
Filter Response Select Pin.
2. S2
Input Multiplexor Select Pin
3. CLK
Sine Wave Clock Input
4. G
Gain Select Pin
5. VDD
Positive
Power
Supply,Typically
2.5
Volts for Split Supply, 5.0 Volts for
Single Supply
6. PD
Power Down Pin, CMOS level,
Hi = Power Down
7, VSS
Negative Power Supply,Typically
2.5
Volts for Split Supply, 0 Volts for
Single Supply
8. F0
Clock to Corner Select Pin
9. GND
GND Pin, OV for Split Supplies
2.5 Volts Typical for Single Supply
10. IN1
Input 1, Select Code 00
11. IN2
Input 2, Select Code 01
12. IN3
Input 3, Select Code 10
13. IN4
Input 4, Select Code 11
14. FSEL
Selects Filter
O = Low Pass, 1 = Bandpass
15. Out
Filter Output
16. S1
Input Multiplexor Select Pin
Pin Configuration
Filter Selection _______________ Gain and Frequency Selection
The Gain control pin G is a tertiary control pin
where state 0 is VSS, state 1 is GND level and
state 2 is VDD.
G
Gain
0
OdB
1
10dB
2
20dB
The frequency control pin F0 is a CMOS level pin
where HIGH is clock to corner of 12.5 to 1 (25
to 1 for Bessel) and LOW is clock to corner of
6.25 to 1 (12.5 to 1 for Bessel). The sample
rate ratio is twice the clock to corner ratio
(double sampling).
FSEL
IN
OUT
GND
TYPE
VSS
CLK
5
VDD
16
15
14
13
12
11
10
9
TYPE
S1
S2
OUT
CLK
FSEL
G
IN4
VDD
IN3
PD
IN2
VSS
IN1
F0
GND
8 Pin
16 Pin
© 2000-2016 Mixed Signal Integration 3



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