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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MSVHFS 데이터시트(PDF) 4 Page - Mixed Signal Integration |
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MSVHFS 데이터시트(HTML) 4 Page - Mixed Signal Integration |
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4 / 9 page  Filter Selection The filter type is selected using the two filter se- lect pins, TYPE and FSEL, FSEL is a CMOS level pin that selects lowpass or bandpass response (lowpass = 0, bandpass = 2). TYPE Is a tertiary control pin that selects the filter response. State 0 is VSS, state 1 is GND and state 2 is VDD. TYPE Lowpass Bandpass 0 Butterworth Full Octave 1 Bessel Third Octave 2 Elliptic Sixth Octave Gain and Frequency Selection The Gain select pin G is a tertiary control pin where state 0 is VSS, state 1 is GND level and state 2 is VDD. G Gain 0 OdB 1 10dB 2 20dB The clock to corner select pin F0 is a CMOS level pin where HIGH is clock to corner of 12.5 to 1 (25 to 1 for Bessel) and LOW is clock to corner of 6.25 to 1 (12.5 to 1 for Bessel). The sample rate ratio is twice the clock to corner ratio (double sampling). ©2011-2 2014 Mixeed Signal Inteegratioon 4 Weeb Sitee ““www.mix-ssig.coom”” 6/2014 Selecttable Very High Frequency LP//BP Filtter Datta Sheett |
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