GPL191B2

© Generalplus Technology Inc.

Proprietary & Confidential

9

Mar. 08, 2010

Version: 1.1

6.10. Watchdog Timer (WDT)

An on chip watchdog timer(WDT) is available in the GPL191B2.

The WDT is designed to recover the system from abnormal

operation.

If the system is stalled, the WDT will generate a

system reset to restart system after one second.

If WDT is

enabled, the WDT should be cleared every 0.5 seconds to avoid

accidental reset. The WDT can be cleared by writing to WDT

clear register. Note that the WDT only works when 32768 Hz

clock is available.

6.11. Mask Options

6.11.1. 32768 oscillator

1). X’TAL

2). R-oscillator

6.11.2. Watchdog timer

1). Enable

2). Disable

6.11.3. TxD/RxD selection

1). TxD as UART transmit output, RxD as UART receive input

2). TxD as I/O port EF4, RxD as I/O port EF5

6.11.4. Port EF bit7 - 0 with 600K, Pull-Low

Each bit can be optioned to Enable/Disable individually.

6.11.5. I/O and LCD driver

There are some examples shown as below:

Dots

Segment

Common

Input/Output

Input/Output

Input/Output

1024

64

16

4 IOEF3 - 0

-

-

960

60

16

4 IOEF3 - 0

4 IOCD3 - 0

-

832

52

16

4 IOEF3 - 0

4 IOCD3 - 0

8 IOAB7 - 0

768

64

12

8 IOEF3 - 0

-

-

Each input/output port, IOAB7 - 0 and IOCD3 - 0, can be optioned

to LCD segments independently, and LCD commons (COM15 - 12)

can be optioned to IOEF7 - 6 when LCD mode is 1/8 duty or 1/12

duty.

If UART is not used, two more I/O ports (TxD/IOEF4,

RxD/IOEF5) can be used.