GPBA02A

© Generalplus Technology Inc.

Proprietary & Confidential

12

JAN. 06, 2011

Version: 1.6

Speed up XOR register timing:

The command byte: C7=1; C6=device option value; C5-4=11;

C3-0=register address. The speed up XOR data byte: D7-0 is

the value that will be XOR with the corresponding 0xH register’s

value and then be written to the corresponding 0xH register. In

speed up XOR register cycles, the output pin (MISO) remains in

high impedance state.

Read register or read IO port timing:

The command byte: C7=0, C6=device option value, C5-4=00,

C3-0=register address. The read data byte: D7-0 is the value

that will be read from the corresponding register or corresponding

IO ports. In read register or IO port cycles, the read data byte is

transmitted via output pin (MISO) during the last 8 SCK clock

cycles. After the 16th SCK clock, MISO remains the value of B0

until CSB is high.

5.3.2. SPI Synchronous Data Timing Specifications

CSB

SCK

MOSI

MISO

valid

data

HI-Z

......

......

......

valid

data

HI-Z