AW33802CSR datasheet(13/20 Pages) AWINIC

13 / 20 page

AW33801/AW33802

AW33805/AW33809/AW33812

Jan 2018 V1.2

www.awinic.com.cn

FUNCTIONAL DESCRIPTION

Device Operation

If the input voltage is between UVLO and OVP threshold, the internal charge pump begins to work after

debounce time, the gate of the nFET switch will be slowly charged high till the switch is fully on. If the input

voltage exceeds the OVP trip level, the switch will be turned off in about 90ns. If input voltage falls below UVLO

threshold, or over-temperature happens, the switch will also be turned off.

Over-Voltage Protection

If the input voltage exceeds the OVP rising trip level, the switch will be turned off in about 90ns. The switch will

remain off until VIN falls below the OVP falling trip level.

OVP Threshold Adjustment

If OVLO pin is not grounded, and by connecting external resistor divider to OVLO pin as shown in the typical

application circuit, between IN and GND, the OVP threshold can be adjusted as following:

VIN_OVLO=

R1+R2

VOVLO_TH

The adjustment range is 4V to 20V. When the OVLO pin voltage VOVLO exceeds VOVLO_SEL(0.26V typical), VOVLO

is compared with the reference voltage VOVLO_TH(1.20V typical for AW33801/AW33805/AW33809/AW33812,

1.23V typical for AW33802) to judge whether input supply is over-voltage. Take AW33801 for example, if we

select R1 = 51k

Ω and R2 = 12.4kΩ, then the new OVP threshold calculated from the above formula is 6.14V.

USB On-The-Go (OTG) Operation

If VIN = 0V and OUT is supplied by OTG voltage, the body diode of the load switch conducts current from OUT

to IN and the voltage drop from OUT to IN is approximately 0.7V. When VIN > VIN_UVLO, internal charge pump

begins to open the load switch after debounce time. After switch is fully on, current is supplied through switch

channel and the voltage drop from OUT to IN is minimum.

PCB LAYOUT CONSIDERATION

To make fully use of the performance of AW338XX, the guidelines below should be followed.

1. All the peripherals should be placed as close to the device as possible. Place the input capacitor CIN on the

top layer (same layer as the AW338XX) and close to IN pin, and place the output capacitor COUT on the top layer

(same layer as the AW338XX) and close to OUT pin.

2. IN pin routing passes through the external TVS firstly, and then connect AW338XX.

3. Red bold paths on figure 4 and 5 are power lines that will flow large current, please route them on PCB as

straight, wide and short as possible.

4. If R1 and R2 are used, route OVLO line on PCB as short as possible to reduce parasitic capacitance.

5. The power trace from USB connector to AW338XX may suffer from ESD event, keep other traces away from

it to minimize possible EMI and ESD coupling.

6. Use rounded corners on the power trace from USB connector to AW338XX to decrease EMI coupling.

AW33802CSR 데이터시트(PDF) 13 Page - Shanghai awinic technology co.,ltd