 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
GD5F1GQ4REFIS 데이터시트(PDF) 21 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
|||||||||||||||||||||||||||||
GD5F1GQ4REFIS 데이터시트(HTML) 21 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
21 / 60 page  SPI(x1/x2/x4) NAND Flash 1G 21 8.7 Read From Cache Quad IO (EBH) The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input the 4 dummy bits, followed a 12-bit column address for the starting byte address and a dummy byte by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out until the boundary wrap bit. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command. Figure8-6. Read From Cache Quad IO Sequence Diagram Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(SIO0) SO(SIO1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 A7-0 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 WP#(SIO2) HOLD#(SIO3) 4 5 6 7 Dummy Byte1 Byte2 dummy<3:0>, A11-A8 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
