GD5F2GQ4RF9JS datasheet(20/57 Pages) GIGADEVICE

부품명	GD5F2GQ4RF9JS

상세설명	SPI(x1/x2/x4) NAND Flash

PDF	57 Pages

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제조업체	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

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SPI(x1/x2/x4) NAND Flash

9.7 Read From Cache Dual IO (BBH)

The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH), followed by a 12bit

column address for the starting byte address and a dummy byte by SIO0 and SIO1, each bit being latched in during the

rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address

byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted

out until the end of whole page.

Figure9-6. Read From Cache Dual IO Sequence Diagram

Command

BBH

CS#

SCLK

SI(SIO0)

SO(SIO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A7-0

Dummy

Byte0

CS#

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SI(SIO0)

SO(SIO1)

SCLK

Byte1

Byte2

Byte3

Byte4

Dummy, A11-8

GD5F2GQ4RF9JS 데이터시트(PDF) 20 Page - GigaDevice Semiconductor (Beijing) Inc.