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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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GD9FS1G8F2ALG 데이터시트(PDF) 40 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD9FS1G8F2ALG 데이터시트(HTML) 40 Page - GigaDevice Semiconductor (Beijing) Inc. |
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40 / 55 page  GD9Fx1GxF2A 40 8.8 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever VCC is below VLKO. WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences. The two-step command sequence for program/erase provides additional software protection. 2.5Vth Vcc(min) VCC 0V Don't care CE WP VIL Vcc(min) Vth don't care VIL Ready Busy VIH don't care Operation 5ms max Figure 30_a: Data protection and Power on/off (3.3V Device) 1.5Vth Vcc(min) VCC 0V Don't care CE WP VIL Vcc(min) Vth don't care VIL Ready Busy VIH don't care Operation 5ms max Figure 30_b: Data protection and Power on/off (1.8V Device) |
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