GD25VQ127CSFS datasheet(20/62 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25VQ127C

Figure9. Read Data Bytes at Higher Speed Sequence Diagram

7.8. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being

latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.

The command sequence is shown in followed Figure 10. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out.

Figure10. Dual Output Fast Read Sequence Diagram

7.9. Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being

latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1

and IO0. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

Command

0BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

Command

3BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Clocks

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