2

AT78C5081

3527AS–NETST–10/04

configure the circuit in certain test modes. The PHY is transparent to SATA traffic and as

a result does not perform scrambling/descrambling, encoding/decoding, or run time dis-

parity check. It does not respond to SATA primitives.

Block Diagram

Parallel to

Serial

Linedriver

Equalizer

Squelch

PLL

Clock &

Data

Recovery

Serial to

Parallel

Bandgap

Reference

Serial

Port

Interface

SDEN

SCLK

SDATA

XIN

TXP

TXN

TX_DATA[19:0]

TBC

RXP

RXN

RBC

RX_DATA[19:0]

COMMA_DETECT

SLV

OOB

COMWAKE

COMRI

PARTIAL

SLUMBER

RESET

RX_TEST

TX_TEST

RX_LOCKED

RX_ERROR

ASIC_CK[1:0]

RREF

CDR_CK[1:0]

CDR_DATA[1:0]

TX_DATA[1:0]

IREF

VREF

REG

TOE

SSC Modulator

ASIC_CK

Generator

COMMA Detect

Control

MODE

TESTCTL

STATUS

POR

TX_CK

STOP

TX_ENABLE

AMUX

ATEST

RX_DATA[1:0]

REALIGN

RBCN

Oscillator

XOUT

DTEST_OUT

TEST_CK