T25D32AFIPR datasheet(24/74 Pages) HMSEMI

24 / 74 page

Table 6.3 Status Register-3 (SR3)

Bits

Field

Function

Type

Default State

Description

HRSW

HOLD# or

RESET#

function

Non-volatile

and Volatile

versions

When HRSW=0, the pin acts as HOLD#; when

HRSW=1, the pin acts as RESET#. HRSW

functions are only available when QE=0.

DRV1

Output Driver

Strength

The DRV1 & DRV0 bits are used to determine

the output driver strength for the Read

operations.

DRV0

HFQ

High

Frequency

Enable Bit

0= High Frequency Mode Disabled

1 = High Frequency Mode Enabled

Reserve

WPS

Write Protect

Selection

Non-volatile

and Volatile

versions

When WPS=0, the device will use the

combination of CMP, SEC, TB, BP[2:0] bits to

protect a specific area of the memory array.

When WPS=1, the device will utilize the

Individual Block Locks to protect any individual

sector or blocks.

Latency

Control

(LC)

Variable SPI

Read Latency

Control

Defines the number of read latency cycles in

Fast Read, Dual Out, Quad Out, Dual IO, and

Quad IO commands. See details in Table 6.5.

Note:

1. LC[1:0] only controls SPI read latency and will be reset to default while switching from QPI to SPI. QPI read latency is set by C0

instruction.

6.2.1 BUSY

BUSY is a read only bit in the status register (SR1[0]) which is set to a “1” state when the device is

executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction.

During this time the device will ignore further instructions except for the Read Status Register instruction (see

tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has

completed, the BUSY bit will be cleared to a “0” state indicating the device is ready for further instructions.

6.2.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (SR1[1]) which is set to a 1 after

executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is written disabled.

A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

6.2.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that

provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers

Command (see tW in Section 8.5). All, none or a portion of the memory array can be protected from Program

and Erase commands (see Section 6.4.2, Block Protection Maps). The factory default setting for the Block

Protection Bits is 0 (none of the array is protected.)

6.2.4 Top / Bottom Block Protect (TB)

The non-volatile Top / Bottom bit (TB SR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0)

protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 6.4.2, Block Protection

Maps. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers Command

depending on the state of the SRP0, SRP1 and WEL bits.

HM25Q128A

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