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P9225-R 데이터시트(PDF) 18 Page - Integrated Device Technology |
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P9225-R 데이터시트(HTML) 18 Page - Integrated Device Technology |
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18 / 34 page ![]() P9225-R Datasheet © 2018 Integrated Device Technology, Inc. 18 November 12, 2018 8.7 Enable Pin – EN ����� The P9225-R can be disabled by applying a logic HIGH to the EN pin. When the EN pin is pulled HIGH, the device is in Shut-Down Mode. Connecting the EN pin to logic LOW activates the device. 8.8 Thermal Protection The P9225-R integrates thermal shutdown circuitry to prevent damage resulting from excessive thermal stress. The thermal protection will shut down the receiver if the die temperature exceeds 140°C. If the die temperature exceeds 130°C, the Thermal_SHTDN_Status flag is set and an End Power Transfer (EPT) packet is sent in order to lower the temperature. 8.9 External Temperature Sensing – TS The P9225-R has a temperature sensor input, TS, which can be used to monitor an external temperature by using a thermistor. The TS pin voltage calculation is described by Equation 1. VTS = VVDD18 × NTC R+NTC Equation 1 where NTC is the thermistor’s resistance and R is the pull-up resistor connected to the VDD18 pin. The over–temperature shutdown is triggered when the TS pin voltage is lower than 0.6V. 8.10 End of Charge – EOC The End-of-Charge (EOC) pin is an active HIGH logic input, which can be used with an application processor or charger IC in battery management applications. When asserted, the receiver issues an End Power Transfer (EPT) packet to the transmitter terminating power transfer. 8.11 Received Power Packet Offset and Gain Calibration – RPPO and RPPG The Received Power Packet Offset (RPPO) and Received Power Packet Gain (RPPG) calibrations utilize dedicated pins for tuning foreign object detection (FOD). Received Power = Gain ×Power+Offset Equation 2 Power = Calculated Rx Power with Default Setting (in mW) Equation 3 Gain = ADCRPPG 1755 where ADCRPPG = INT �VRPPG 2.1V ×4095� Equation 4 Offset = ADCRPPO −1755(inmW) where ADCRPPO = INT �VRPPO 2.1V ×4095� Equation 5 To use the default FOD setting, set Gain to 1 and Offset to 0. That is equivalent to 0.9V at both RPPO and RPPG pins. To disable the FOD, the RPPO and RPPG pins must be pulled down to GND. |
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