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AD4112BCPZ 데이터시트(PDF) 58 Page - Analog Devices |
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AD4112BCPZ 데이터시트(HTML) 58 Page - Analog Devices |
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58 / 58 page ![]() AD4112 Data Sheet Rev. A | Page 58 of 58 OUTLINE DIMENSIONS 0.50 BSC BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 0.30 0.25 0.18 6.10 6.00 SQ 5.90 1.00 0.95 0.85 0.45 0.40 0.35 0.20 MIN 4.70 4.60 SQ 4.50 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5 40 1 11 10 20 21 30 31 SIDE VIEW EXPOSED PAD SEATING PLANE P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) DETAIL A (JEDEC 95) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PIN 1 INDICATOR AREA Figure 59. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.95 mm Package Height (CP-40-15) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD4112BCPZ −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15 AD4112BCPZ-RL7 −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15 EVAL-AD4112SDZ Evaluation Board EVAL-SDP-CB1Z Evaluation Controller Board 1 Z = RoHS Compliant Part. ©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16465-0-2/19(A) |
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